In the era of Internet of Things, the battery life of edge devices must be extended\nfor sensing connection to the Internet. We aim to reduce the power\nconsumption of the microprocessor embedded in such devices by using a\nnovel dynamically reconfigurable accelerator. Conventional microprocessors\nconsume a large amount of power for memory access, in registers, and for the\ncontrol of the processor itself rather than computation; this decreases the\nenergy efficiency. Dynamically reconfigurable accelerators reduce such redundant\npower by computing in parallel on reconfigurable switches and\nprocessing element arrays (often consisting of an arithmetic logic unit (ALU)\nand registers). We propose a novel dynamically reconfigurable accelerator\nââ?¬Å?DYNaSTAââ?¬Â composed of a dynamically reconfigurable data path and static\nALU arrays. The static ALU arrays process instructions in parallel without\nregisters and improve energy efficiency. The dynamically reconfigurable data\npath includes registers and many switches dynamically reconfigured to resolve\noperand dependencies between instructions mapped on the static ALU array,\nand forwards appropriate operands to the static ALU array. Therefore, the\nDYNaSTA accelerator has more flexibility while improving the energy efficiency\ncompared with the conventional dynamically reconfigurable accelerators.\nWe simulated the power consumption of the proposed DYNaSTA accelerator\nand measured the fabricated chip. As a result, the power consumption\nwas reduced by 69% to 86%, and the energy efficiency improved 4.5 to 13\ntimes compared to a general RISC microprocessor.
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